Algorithm

FPGA Device

Structure

Data Block/Key length

Nr

# of slices

Freq (MHz)

Throughput

(Mbits/sec)

Thr./Area

Mbits/sec/slice

Bit/Slice

# KAMAR

(Proposed

Algorithm)

XC4VLX25

Feistel

128/128

16

312

550

2200

7.05

0.410

AES [17]

XCV100E

Non-Feistel

128/128

10

1125

161

215

0.19

0.114

AES [18]

XCV3200E

Non-Feistel

128/128

10

1769

167

2085

1.18

0.072

SEA [19]

XC4VLX25

Feistel

126/126

117

438

241

260

0.59

0.288

SEA [20]

XC4VLX25

Feistel

126/126

117

360

189

203

0.56

0.350

#L2DCASKE

XC4VLX25

Non-Feistel

128/128

12

336

334

2673

7.95

0.381

#AES

XC4VLX25

Non-Feistel

128/128

10

606

214

2743

4.52

0.211

#DESXL

XC4VLX25

Feistel

64/56

16

323

260

1039

3.21

0.198

#PRESENT

XC4VLX25

Feistel

64/80

31

266

436

901

3.38

0.241

#XTEA

XC4VLX25

Feistel

64/128

32

285

210

421

1.47

0.224