# | Event Name | Description | Range, (μops) |
0 | UOPS_RETIRED | counter for μops retired | 9.159146e7 - 8.133418e9 |
1 | MEM_LOAD_UOPS_RETIRED.LLC_MISS | miss in last-level L3 cache (LLC) | 1.0e−6 - 1.7e−2 |
2 | BR_INST_RETIRED.ALL_BRANCHES | all (macro) branch instructions retired | 3.5e−3 - 2.5e−1 |
3 | BR_MISP_RETIRED.ALL_BRANCHES | all mispredicted macro branch instructions retired | 3.0e−6 - 6.1e−3 |
4 | LONGEST_LAT_CACHE.MISS | core-originated cacheable demand requests that missed LLC | 2.0e−6 - 3.1e−2 |
5 | LONGEST_LAT_CACHE.REFERENCE | core-originated cacheable demand requests that refer to LLC | 2.4e−6 - 1.0e−1 |
6 | MEM_UOPS_RETIRED.ALL_LOADS | counter for load μops retired | 2.8e−4 - 2.14e0 |
7 | MEM_UOPS_RETIRED.ALL_STORES | counter for store μops retired | 1.3e−3 - 1.1e0 |
8 | OFFCORE_REQUESTS.ALL_DATA_RD | demand and prefetch data reads | 1.3e−5 - 1.4e0 |
9 | RESOURCE_STALLS.ANY | resource-related stall cycles | 1.0e−5 - 5.6e−2 |