S. NO

CMOS Circuit

Existing Design Energy in nano joules

Proposed Design-1 Energy in nano joules

Proposed Design-2 Energy in nano joules

1

NOT Gate

2.88

1.50

1.36

2

AND Gate

0.490

0.258

0.248

3

OR Gate

0.688

0.372

0.364

4

NAND Gate

0.423

0.225

0.208

5

NOR Gate

0.417

0.246

0.241

6

EX-OR Gate

1.38

0.733

0.736

7

Full Adder

97.20

6.38

6.28

8

Carry Look Ahead Adder

73.20

5.34

5.41

9

Ripple Carry Adder

30.00

19.79

14.08

10

Carry Select Adder

79.80

52.68

42.60

11

D Flip Flop

21.60

2.14

3.87

12

SR Latch

0.436

0.316

0.308

13

Shift Register

61.00

41.09

39.05

14

Novel Low Power FA 180 nm

6.13

3.79

3.59

15

Novel Low Power FA 90 nm

0.240

0.138

0.137

16

Novel Low Power FA 45 nm

0.040

0.030

0.030

17

Peres gate

2.45

1.47

1.45

18

Feynman Gate

1.98

1.37

1.34

19

Fredkin Gate

9.24

5.40

5.28

20

C17-ISCAS85

7.20

6.32

5.80

21

S27

240

24.7

41.2