Output Voltage

Level

V_out

Switching sequence of proposed MLI

First Half Bridge (HB1)

Second Half Bridge (HB2)

S1

S2

S3

S4

S1

S2

S3

S4

4 V_dc

1

0

0

1

1

0

0

1

3 V_dc

0

1

0

1

1

0

0

1

2 V_dc

0

1

1

0

1

0

0

1

1 V_dc

1

0

0

1

0

1

0

1

0

0

1

0

1

0

1

0

0

−1 V_dc

0

1

1

0

0

1

0

1

−2 V_dc

1

0

0

1

0

1

1

0

−3 V_dc

0

1

0

1

0

1

1

0

−4 V_dc

0

1

1

0

0

1

1

0