Proposed Multiplication structure | Designs taken for comparison and analysis purpose | Number of bits (Nb) | Percentage of parameter values saved (%) | |
Delay | Area | |||
TVL based RLNS scheme | Existing technique [54] | 8 | 99.4 | 89 |
16 | 98.6 | 80 | ||
32 | 98.2 | 85 | ||
Binary logic based RLNS design | 8 | 97.9 | 54 | |
16 | 95.1 | 37 | ||
32 | 93.3 | 30 |