Signal

Type

Description

ADD [24:0]

Input

Address bus from processor.

WR_L

Input

Write strobe from processor.

BYTE_EN [3:0]

Input

Byte enable signals from processor.

TERM_L

Input

Terminate signal from processor.

SDRAM_CYCLE [3:0]

Input

State machine bits—indicates the type of cycle: 00 = idle, 01 = command, 10 = data, 11 = refresh.

STATE_CNTR [3:0]

Input

State machine bits—indicates state of cycle.

SDRAM_MODE_REG [11:0]

Input

Mode Register Value.

SDRAM_CMND [1:0]

Input

SDRAM command desired: 00 = nop,

01 = precharge, 10 = autorefresh,

11 = load mode register.

CLK

Input

Clock signal.

RST_L

Input

Reset signal.

SD_CKE

Output

SDRAM Clock Enable signal.

SD_BA [1:0]

Output

SDRAM Bank Address signals.

SD_CS0_L

Output

SDRAM Chip Select signal for lower 16 MB region.

SD_CS1_L

Output

SDRAM Chip Select signal for upper 16 MB region.

SD_RAS_L

Output

SDRAM Row Address Strobe.

SD_CAS_L

Output

SDRAM Column Address Strobe.

SD_WE_L

Output

SDRAM Write Enable Strobe.

SD_ADD [11:0]

Output

SDRAM Address Signals.

SD_DQM [3:0]

Output

SDRAM Data Qualifier Mask.

ACK_L

Output

Acknowledge—indicates when data cycles are active.