Signal

Type

Description

SDRAM_CS_L

Input

SDRAM Chip Select from processor.

WR_L

Input

Write pulse from processor.

SDRAM_EN

Input

SDRAM Enable signal—may be tied high.

TERM_L

Input

Terminates burst cycles.

CLK

Input

Input clock signal.

RST_L

Input

Reset signal.

BYTE_EN [3:0]

Input

Byte enable signals.

ADD [24:0]

Input

Processor Address bus. Used to address SDRAM.

SD_CKE

Output

SDRAM Clock Enable signal.

SD_BA [1:0]

Output

SDRAM Bank Address signals.

SD_CS0_L

Output

SDRAM Chip Select signal for lower 16 MB region.

SD_CS1_L

Output

SDRAM Chip Select signal for upper 16 MB region.

SD_RAS_L

Output

SDRAM Row Address Strobe.

SD_CAS_L

Output

SDRAM Column Address Strobe.

SD_WE_L

Output

SDRAM Write Enable Strobe.

SD_ADD [11:0]

Output

SDRAM Address Signals.

SD_DQM [3:0]

Output

SDRAM Data Qualifier Mask.

ACK_L

Output

Acknowledge—Indicates when data cycles are active.

SDRAM_SETUP

Output

SDRAM Setup indicates that the SDRAM has been initialized.