Scheme
Area
Delay
[8]
76 n + ( 33 / 2 ) n log 2 n
6 log 2 n + 23
[3]
37 n + 18
16 n + log 2 n + 13
Proposed I
46 n + 15 log 2 n + 10
4 log 2 n + 7
Proposed II
109 n + 15 log 2 n + 24
4 log 2 n + 16