| Technique | No. of MOS’s | Merits | Demerits | Limitations |
| Biasing techniques | ||||
| Reverse body biasing [57] [58] [63] [65] [107] [108] | 6T | ISub-th ↓↓ | IJunction↑, Large transition delay | Sensitive to VTH variation & GIDL |
| Forward body bias, [59] [60] [68] [69] [70] | 6T | Small switching capacitance, speed ↑ | Process complexity, Area overhead | Sensitive to SCE & DIBL |
| Source-biasing [61] [109] [110] | 6T | ISub-th, IGate ↓↓ | Delay penalty (τPD ↑) | Impact on soft error rate (SER) |
| Dual-VTH [71] | 6T | Improved short-channel, DIBL | Switching | Need of FBB |
| VTCMOS [72] [73] | 6T | Low leakage, high speed | Additional circuitry need to control the threshold | Need to control the body bias |
| Clamping diode [74] | 8T | ISub-th, IGate ↓ | Delay penalty (τPD ↑) | Floating voltage at VSL |
| Stacking body biasing (SRB) [75] | 8T | ISub-th, IGate ↓ | Delay increase, Area overhead | VTH ↑ due to body effect |
| Power gating techniques | ||||
| Ground gated, sleep transistor [79] [80] [82] | 8T | ISub-th, IGate ↓ | virtual ground ↑↑, PD path resistance ↑ | process-induced Vt variation, data retention problem |
| Data retention gated-ground [83] | 7T | data retention, low leakage | Delay penalty | Need of External control signal |
| N-control with gated-VDD [84] | 8T | leakage power, high speed | Dual-threshold | Need to control virtual ground |
| Diode-connected [85] [88] | 8T | ISub-th, IGate ↓ | SNM ↓, sensitive to NBTI/PBTI | Data recalled, need of SBT |
| programmable bias transistor [90] | 8T | Good control in virtual ground, | die-to-die, within die temperature variations | Need of PBT |
| Active feedback op-amp [91] | 7T+ op-amp | Standby power ↓, die-to-die leakage ↓ | DC power consumed by the op-amp, area | Need of op-amp |
| Light sleep mode [92] | 9T | Low leakage power, data retained | performance degradation, area | Memory voltage > min. data retention voltage |
| Shutdown mode design [92] | 11T | Low leakage power | Increased virtual ground, area | Need more no. of control inputs |
| Multi-threshold design | ||||
| Basic Asymmetric [97] [98] | 6T | reduces leakage power by 70x | bit-line discharge time ↑ | Need of high-VTH |
| High-VTH on RBL Sensing [100] | 8T | good Ion and Ioff current ratios | Read access time ↑ | Small prominent in near and sub-threshold region |
| Low-VTHon RBL Sensing [100] [102] | 8T | larger read bit-line swing | Isub-th ↑ | smaller read bit-line data sensing margin |
| Bit-line boosting [103] [104] | 9T | low leakage, read bit-line sensing margin ↑ | Data dependent bit line- leakage ↑ | Data effected due to Temperature variations |
| Supply Feedback approach [105] [106] | 9T | Improved write margin & functionality | Performance degradation | Need to maintain a reasonable SNM. |