|
| This work | Result reported in [7] | Result reported in [6] | Result reported in [8] | |
| Traditional self biased PLL | Dual loop self biased PLL | ||||
| Output frequency (MHz) | 2720 | 2720 | 3100 | 2100 | 700 |
| Reference (MHz) | 170 | 170 | 108 | 65.6 | 1 |
| Tuning range (GHz) | 0.8 - 3.2 | 0.8 - 2.8 | 1.4 - 3.2 | 0.86 - 2.1 | - |
| KVCO (MHz/V) | 3600 | 470 | 10 | - | 350 |
| Lock time (frequency step) | 0.16 μS (1.4 GHz) | <1 μS (710 MHz) | 85 μS (940 MHz) | <3 μS (1.3 GHz) | - |
| RMS jitter (pS) | 1.6 (0.0043UI) | 0.8 (0.0022UI) | 1.01 (0.0031UI) | 1.37 (0.0028UI) | 1.32 (0.0009UI) |
| Power (mW) | 35.0 | 35.8 | 27.5 | 5.3 | - |
| FOM (dB) (as in [7] ) | −220.7 | −226.8 | −225.5 | −230 | - |
| Supply voltage | 1.8 | 1.8 | 1.2 | 1.8 | - |
| Technology (nm CMOS) | 180 | 180 | 65 | 180 | - |