| PAPERS | [1] | [3] | [13] | [4] | [5] | PROPOSED | |||
| Algorithm | Optimized FSD-B | K-Best SD | PIPSD | FSD 2 | LFSD (16,221) | SOCA | PCA | CELLA | |
| FPGA | Xilinx XC2VP70 | Xilinx XC2VP30 | Virtex 6 XC6VLX240T | Xilinx XC2VP70 | Xilinx Virtex 5 XC5VSX240T | ||||
| Modulation | 16 QAM | 16 QAM | 16 QAM | 16 QAM | 16 QAM | 16 QAM | 64 QAM | ||
| SLICES (Available) | 24,815 (33,088) | 8778 (13,696) | NR | 12,721 (33,088) | 13,577 (37,440) | 9570 (37,440) | 9471 (37,440) | 2215 (37,440) | 8913 (37,440) |
| FFs (Available) | 39,800 (66,176) | 6274 (27,392) | NR | 15,332 (66,176) | 32,934 (149,760) | 23,133 (149,760) | 22,814 (149,760) | 4918 (149,760) | 16,850 (149,760) |
| LUT (Available) | 31,759 (66,176) | 13,417 (27,392) | NR | 16,119 (66,176) | 34,378 (149,760) | 24,523 (149,760) | 24,126 (149,760) | 4982 (149,760) | 16,132 (149,760) |
| DSP (Available) | NR | 48 (136) | NR | NR | 348 (1056) | 174 (1056) | 174 (1056) | 38 (1056) | 151 (1056) |
| BRAM (Available) | NR | NR | NR | 82 (328) | 99 (516) | 70 (516) | 70 (516) | 18 (516) | 67 (516) |
| Latency (cycles) | 78 | NR | NR | NR | 63 | 133 | 109 | 14 | 53 |
| Fclock | 150 MHz | NR | 178 MHz | 150 MHz | 150 MHz | 150 MHz | 150 MHz | ||
| Throughput at 20 db (Mbps) | 450 Mbps | 732 Mbps | 356 Mbps | 600 Mbps | NR | NR | 400 Mbps | 970 Mbps | 830 Mbps |
| Power (mw) | NR | 165 | NR | NR | NR | NR | NR | 40 mw | 141 mw |