S.NO

CMOS Circuit

Existing Design Delay in Pico seconds

Proposed Design-1

Delay in Pico seconds

Proposed Design-2

Delay in Pico seconds

1

NOT Gate

26.56

25.98

26.02

2

AND Gate

20.06

20.06

20.06

3

OR Gate

40.01

39.21

39.85

4

NAND Gate

20.05

20.05

20.05

5

NOR Gate

49.41

47.77

48.42

6

EX-OR Gate

65.15

65.23

65.27

7

Full Adder

140.30

140.25

141.60

8

Carry Look Ahead Adder

142.90

142.79

142.88

9

Ripple Carry Adder

139.10

138.92

139.12

10

Carry Select Adder

599.70

598.99

600.20

11

D Flip Flop

81.19

81.02

81.15

12

SR Latch

10,020

10,040

10,020

13

Shift Register

9800

9788

9802

14

Novel Low Power FA 180 nm

80.71

80.59

81.02

15

Novel Low Power FA 90 nm

40.92

40.82

41.03

16

Novel Low Power FA 45 nm

14.31

14.19

14.20

17

Peres Gate

36.29

36.19

36.32

18

Feynman Gate

36.09

36.09

36.22

19

Fredkin Gate

10,070

10,069

10,072

20

C17-ISCAS85

10,050

10,051

10,051

21

S27

30,020

30,022

30,025