Multiplication structure

Area (µm²)

Total Power Dis

sipation (µW/mW)

Delay

(ns)

PDP (×10⁻¹⁵ Joules)

Technique used

Number of trits/bits

(N_t/N_b)

TVL based RLNS scheme

6

12,536

3.96^*

2.5

9.9

11

19,910

15.7^#

9.2

144,440

21

31,734

36.5^#

15.5

492,750

Binary logic based RLNS scheme

8

27,208

1.86^*

123

228.78

16

31,761

3.29^*

188

618.52

32

45,184

4.53^*

232

1050.96

Based on Radix-8 booth encoding technique [54]

8

117,676

15.97^*

443

7074.71

16

164,997

32.17^*

697

22,422.4

32

215,781

53.25^*

885

47,126.2