Architecture Model

No of Slice

No of Slice LUT

No of IOB

Total Power (mw)

Clock Power (mw)

Logic Power (mw)

Signal Power (mw)

Quiescent Power (mw)

M. Litochevski et al. Design [21]

1533

3635

523

1454

38

35

38

1343

H. Sathyanarayana’s Design [22]

789

11275

262

1473

28

28

74

1343

Proposed Design

955

2202

391

815

32

20

37

722