|
| SML1 | SML2 | Path | Key Node Voltage | Results | |||||
| S1 | S2 | P | MML | SML1 | SML2 | FML | ||||
| Case 1 | Match | Match | X | X | X | VDD | 0 | 0 | VDD | Match |
| Case 2 | Mismatch | Match | O | X | O | 2/3VDD | 2/3VDD | 0 | 0 | Mismatch |
| Match | Mismatch | X | O | O | 2/3VDD | 0 | 2/3VDD | 0 | Mismatch | |
| Case 3 | Mismatch | Mismatch | O | O | O | 1/2VDD | 1/2VDD | 2/3VDD | 0 | Mismatch |